1. Field of the Invention
The present invention relates to a dynamic adder with Manchester carry architecture that provides improved generate function control.
2. Discussion of the Prior Art
Computational processes can be performed by electrical circuits which are combinations of basic binary units such as flip-flops, AND gates, OR gates and invertors. Thus, while circuits can be designed to perform addition, adder circuits are much more complicated than most computational circuits because of the "carry" problem.
High speed, digital systems perform addition on parallel words of typically 8 to 64 bits. The result of an addition at any bit position depends not only on the two operand bits in that position but also on the result of the addition of the less significant operand bits. More specifically, the result depends on the "carry" from the less significant bit positions.
In general mathematical terms, the addition process for bit position n+1 of terms A and B involves adding the operands A.sub.n +1 and B.sub.n +1 and the carry C.sub.n. The result is a digit for the sum and possibly a digit to be carried, i.e. carry C.sub.n +1 Thus, for example, a 4-bit adder has inputs A.sub.1 A.sub.2 A.sub.3 A.sub.4, B.sub.1 B.sub.2 B.sub.3 B.sub.4 and carry-in C.sub.n ; it provides outputs .SIGMA..sub.1 .SIGMA..sub.2 .SIGMA..sub.3 .SIGMA..sub.4 and carry-out C.sub.n +4.
In the simplest adder scheme, ripple carry addition, each bit position receives a potential carry input from the less significant position and passes a potential carry on to the more significant position. The worst-case delay for the addition of two n-bit numbers using the ripple carry method is n-1 carry delays plus one sum delay. Thus, the ripple carry technique uses a minimum amount of circuitry, but is rather slow.
Addition can be made much faster if more logic is used at each bit position to anticipate the carry into this position instead of waiting for a ripple carry to propagate through all the lower positions. An adder designed to include carry anticipation is called a carry lookahead adder.
Adder carry delay grows linearly with the size of the input word. Carry lookahead adders improve this delay by calculating the carry to each stage of the adder in parallel.
The carry of the ith stage, C.sub.i, may be expressed as EQU C.sub.i = G.sub.i + P.sub.i .multidot. C.sub.i -1 (1)
where EQU G.sub.i = A.sub.i .multidot. B.sub.i generate signal. (2) EQU P.sub.i = A.sub.i .sym. B.sub.i propagate signal. (3)
Expanding this yields
C.sub.i = G.sub.i + P.sub.i G.sub.i-1 + P.sub.i P.sub.i-1 G.sub.i-2
+... + P.sub.i ...P.sub.i C.sub.0. ( 4)
The sum S.sub.1 is generated by ##EQU1##
It is clear from the above that the size of the gates needed to implement this carry lookahead scheme can become quite large. As a result, the number of stages of lookahead is usually limited. For four stages of lookahead, the appropriate terms are ##EQU2##
A possible implementation of a carry gate for this kind of carry lookahead adder for 4 bits is shown in FIG. 1. Note that the gates have been partitioned to keep the number of inputs less than or equal to four. The circuit and layout for this design are quite irregular. The carry-out term C.sub.4 may be expressed as EQU C.sub.4 = G.sub.4 +P.sub.4 .multidot.(G.sub.3 +P.sub.3 .multidot.(G.sub.2 +P.sub.2 .multidot.(G.sub.1 +P.sub.1 .multidot.C.sub.0))) (6)
This function may be implemented as a domino CMOS gate, as shown in FIG. 2. Carry C.sub.1 -C.sub.3 are generated similarly. Note that the worst-cast delay path in this circuit has six N-channel transistors in series.
The efficiency of the domino carry chain shown in FIG. 2 can be enhanced by precharging at appropriate points. The elemental circuit for accomplishing this is shown in FIG. 3A. Operation of the FIG. 3A circuit proceeds as follows. When CLOCK is low, the output node is precharged by the P-channel pull-up transistor. When CLOCK goes high, the N-channel pull-down transistor turns on. If carry generate (A.multidot.B), i.e. signal G, is true, then the output node discharges. If carry propagate (A .sym. B) is true, then a previous carry may be coupled to the output node, conditionally discharging it.
A 4-bit adder can be constructed by cascading four such stages and constructing the circuitry to supply the appropriate signals. This is commonly called a Manchester carry adder. Thus, a 4-bit Manchester carry adder would be constructed as shown in FIG. 3B. The adder circuit shown in FIG. 3B is similar to the domino carry circuit shown in FIG. 2. However, the intermediate carry gates are no longer needed since the carry values are available in a distributed fashion. As further shown in FIG. 3B, if all propagate signals are true, and C is high, six series N-channel transistors pull the output node down. Thus, the worst-case propagation time can be improved by bypassing the four stages if all carry propagate signals are true.